A NAND-type flash memory has been known as an electrically erasable programmable and highly integrable memory (EEPROM). The NAND-type flash memory forms a NAND cell unit including a plurality of memory cells connected serially in such a manner that adjacent memory cells share a source/drain diffused layer. Both ends of the NAND cell unit are connected via respective selection gate transistors to a bit line and a source line, respectively. Such the configuration of the NAND cell unit allows for a smaller unit cell area and larger capacity storage than the NOR type.
A memory cell in the NAND-type flash memory has a charge accumulating layer (floating gate) formed on a semiconductor substrate with a tunneling insulator interposed therebetween, and a control gate layered on the floating gate with an intergate insulator interposed therebetween. It is operative to store data nonvolatilely in accordance with the state of charge accumulated in the floating gate. Specifically, a state with a higher threshold voltage after electrons are injected into the floating gate is used as data “0”, for example, while a state with a lower threshold voltage after electrons are released from the floating gate is used as data “1”, thereby storing binary data. Recently, a write threshold distribution has been fragmented to store multivalued data such as 4-valued one.
Writing data in the NAND-type flash memory is executed on a page basis with one page including all (or half of) memory cells arrayed along a selected word line. Specifically, writing is executed as operation to apply a write (program) voltage Vpgm to the selected word line to inject FN tunneling electrons from a cell channel into the floating gate. In this case, the potential on the NAND cell channel can be controlled from a bit line in accordance with write data “0”, “1”.
In the case of “0” write, Vss is applied to the bit line to transfer Vss via the turned-on selection gate transistor to the channel in the selected cell. In this case, a larger electric field is placed across the floating gate and the channel in the selected cell to inject electrons into the floating gate. On the other hand, in the case of “1” write (non-write), Vdd is applied to the bit line to charge the NAND cell channel up to Vdd−Vth (Vth is a threshold voltage of the selection gate transistor) to bring it into the floating state. In this case, the potential on the cell channel is elevated through capacitive coupling with the word line to inhibit injection of electrons into the floating gate.
If the cell channel voltage is boosted insufficiently in a Vpgm-given “1”-written cell (non-written cell), electrons are injected into the floating gate to cause an undesired threshold fluctuation (erroneous write). Non-selected word lines are usually given a write pass voltage (middle voltage) Vm lower than the write voltage Vpgm to control the channel voltage in the NAND cell unit, thereby preventing injection of electrons into the floating gate in the “1”-written cell. Sufficient channel boosting in the selected cell usually requires an increase in Vm, which contrarily causes weak write in non-selected cells in the NAND cell unit including a “0”-written cell and accordingly requires an optimization of Vm.
Until now, channel voltage control schemes on writing for preventing erroneous write in “1”-written cells and non-selected cells in the NAND-type flash memory have been proposed as follows.
(1) A self-boost (SB) scheme, which brings all channels in the NAND cell unit into the floating state on “1” writing to boost the channels with capacitive coupling with word lines.
(2) A local self-boost (LSB) scheme, which separates a channel in a selected cell from others on “1” writing to boost only that channel.
(3) An erase area self-boost (EASB) scheme, which is premised on sequential writing executed by writing to memory cells in turn from the source line side, and which separates the non-written area including the selected cell from the written area to boost the non-written area.
Even the use of such the channel voltage control schemes may cause a problem in accordance with further developed fine patterning of the NAND-type flash memory. The problem is associated with erroneous write in a cell adjacent to a selection gate transistor (in particular, the selection gate transistor close to the source line). On data writing, the selection gate transistor close to the source line is kept in the off state with the gate voltage of 0 V. If an adjacent cell is a “1”-written cell (non-written cell) given the write voltage Vpgm, a gate-induced drain leakage (GIDL) current occurs at the drain end of the selection gate transistor. In this case, erroneous write occurs such that electrons are injected into the floating gate in an adjacent non-written cell. Similar erroneous write may arise possibly if the cell adjacent to the selection gate transistor is given the write pass voltage Vm (<Vpgm).
Also in the cell adjacent to the selection gate transistor close to the bit line, similar erroneous write occurs.
To prevent the erroneous write due to the GIDL current, there are considered a design to suppress the GIDL current at the drain end of the selection gate transistor (for example, an improvement in channel profile), a design to suppress injection of hot electrons due to GIDL (for example, an elongated distance between the selection gate transistor and the memory cell), and so forth. These measures can not become effective solutions, however, if minimum process dimensions are increasingly made smaller.
For the above erroneous write, a scheme is effective to a certain extent, in which a dummy cell unavailable for data storage is arranged adjacent to the selection gate transistor. For example, it is disclosed in Japanese-Patent Laying-open publication No. 2006-186559, which is incorporated herein by reference.
The so-called soft-programming scheme has been known to dissolve an over-erased state in erased cells after collective erasing. For example, it is disclosed in Japanese Patent Laying-open publication No. 2006-59532, which is incorporated herein by reference. This scheme can narrow the threshold range of data as a whole and accordingly it is critical to preventing data from varying due to capacitive coupling between floating gates in adjacent cells. It is particularly critical as an anti-erroneous write technology in an increasingly fine-patterned NAND-type flash memory, and in a multivalued NAND-type flash memory, most of all.